CCD solid-state imagers are broadly used, as image input terminals, not only in digital still cameras (DSCs) but also in digital video cameras (DVCs), PC cameras and PDA terminal cameras, for example. Meanwhile, CCD solid-state imagers include, in kind, FF (full frame)-CCDs, FT(frame transfer)-CCDs, IT(interline transfer)-CCDs and FIT-(frame interline transfer)-CCDs.
For example, the IT-CCD area sensor has a multiplicity of photocells (sensor sections) arranged in a two-dimensional matrix form (rows). A plurality of vertical transfer CCDs (V registers) are arranged respectively between vertical columns of photocells, to provide a structure having, usually, one line of horizontal transfer CCDs adjacent to transfer destination ends of vertical transfer CCDs. The IT-CCD area sensor uses a two-phase, three-phase or four-phase drive scheme in transfer-driving the vertical transfer CCDs, wherein the storage modes include a field storage mode and a frame storage mode.
FIG. 1 is a schematic diagram showing a related art of a solid-state imager configured with a CCD solid-state imaging device and an external circuit. The CCD solid-state imaging device 3 configuring the solid-state imager 1 has, on a semiconductor substrate 10, a multiplicity of sensor sections (photocells) 20, e.g. of photodiodes as an example of light-receiving elements corresponding to a pixel (unit cell), arranged vertically (rows) and horizontally (columns) in a two-dimensional matrix form. The sensor sections 20 convert the light incident on a light-receiving surface into a signal charge in an amount commensurate with the light quantity thereof, and store it thereon.
Meanwhile, the CCD solid-state imaging device 3 is arranged with V registers (vertical CCDs, vertical transfer sections) 30, corresponding to the respective vertical rows of sensor sections 20, having a plurality (in this example, three per unit cell) of vertical transfer electrodes Vφ1-Vφ3 corresponding to the three-phase driving.
Each vertical transfer electrode Vφ1-Vφ3 (denoted with the same references as the vertical transfer pulses hereinafter referred) has a repetition in transfer direction based on one pixel (i.e. unit cell) of the sensor section 20. Transfer is vertical in FIG. 1, in which direction the V registers 30 are arranged. Furthermore, between the V register 30 and the sensor section 20, a read-out gate terminal ROG is interposed. Channel stops CS are provided in each boundary between the unit cells.
Furthermore, an H register (horizontal CCD, horizontal transfer section) 40 is provided in one line extending left and right in the figure in a position adjacent to the transfer-destination ends of a plurality of the V registers 30. The H register 40 has, at its transfer-destination end (left in the figure), an output section (output buffer circuit) 50, e.g. in a floating diffusion amplifier configuration. The output section 50 converts the signal charge sequentially injected from the H register 40 into a signal voltage for output.
A drain voltage VDD, gate voltage VGG and reset drain voltage VRD are applied to the CCD solid-state imaging device 3 from a drive power source 70 configuring an external circuit 5.
The signal charge stored on each sensor section 20 is read onto the V register 30 through the read-out gate terminal ROG by deepening the potential on the gate terminal electrode due to application of a read pulse XSG, issued from a timing generator 80 configuring the external circuit 5, to the gate terminal electrode of the read-out gate terminal ROG.
The V register 30 is transfer-driven on an all-pixel read-out scheme (non-interlace scheme),e.g. due to three-phase vertical transfer pulses Vφ1-Vφ3 mutually different in phase corresponding to the vertical transfer electrodes Vφ1-Vφ3. The signal charge read out of each sensor section 20 is sequentially, vertically transferred to the H register 40 in an amount corresponding to one scanning line (one line) at one time in a part of horizontal blanking period. Note that the configuration may be by two-phase or four-phase driving without limited to three-phase.
The H register 40 sequentially, horizontally transfers to the output section 50 the signal charge corresponding to one line vertically transferred from each of the V registers 30, on the basis of two-phase horizontal transfer pulses Hφ1, Hφ2 issued from the timing generator 80.
The output section 50 stores the signal charge sequentially injected from the H register 40 to a not-shown floating diffusion, and converts the stored signal charge into a signal voltage. The signal voltage is outputted as an imaging signal (CCD output signal) through a not-shown output circuit of a source follower configuration, under the control of a reset pulse φRG issued from the timing generator 80.
Namely, in the CCD solid-state imaging device 3, the signal charge detected in the image area arranging the sensor sections 20 vertically and horizontally in a two-dimensional form is vertically transferred to the H register 40 by the V register 30 provided correspondingly to the vertical columns of sensor sections 20. The signal charge is then horizontally transferred by the H register 40. Then, a potential is caused correspondingly to the signal charge from the H register 40 and outputted through the output section 50, which operation is repeated.
FIG. 2 is a circuit diagram showing a configuration example of the output section 50 in the CCD solid-state imaging device. The output section 50 configures a front-staged output section (preamplifier) of an incorporated type in the CCD solid-state imaging device. This has a three-stage source follower (current amplifier circuit) configuration having drive MOS transistors (DM: Drive MOS) DM1, DM2, DM3 and load MOS transistors (LM: Load MOS) LM1, LM2, LM3, to provide a signal converting section 52 for converting the signal charge from the H register 40 into a voltage signal. Meanwhile, the output section 50 has a reset gate terminal MOS transistor (RGTr) 54 to control the signal converting section 52 on the basis of a reset pulse ORG corresponding to a horizontal transfer clock.
In the signal converting section 52, there are provided a plurality of stages of amplifier circuits, connecting respectively between the source terminals of the drive MOS transistors DM1, DM2, DM3 and the drain terminals of the load MOS transistors LM1, LM2, LM3, at from an input stage over to an output stage of the signal converting section 52.
The drive MOS transistor DM1 at the extreme input stage initial stage, of among the drive MOS transistors DM1, DM2, DM3 forming the source follower circuit drive transistors, has a gate terminal connected to a floating diffusion terminal FD to be supplied with a signal charge from the H register 40. This is connected with a source terminal of a reset gate terminal MOS transistor 54.
The drain terminal of the same is connected to a power source VDD terminal, e.g. approximately +15 V. The source terminal is connected to a drain terminal of a load MOS transistor LM1 serving as current supplier to the drive MOS transistor DM1. The reset gate terminal MOS transistor 54 has a gate terminal to be supplied with a reset pulse φRG corresponding to a horizontal synchronization clock from the timing generator 80, and a drain terminal applied with a reset drain voltage VRD.
The load MOS transistor LM1 has a gate terminal to receive a constant voltage VGG, e.g. approximately 5 V, as a gate terminal bias voltage, and a source terminal grounded through a fixed resistance RSS. The MOS transistors DM1, LM1 and the fixed resistance RSS constitute a first-staged source follower circuit.
The source terminal of the drive MOS transistor DM1 is further connected to a gate terminal of a drive MOS transistor DM2 as a drive transistor in the next-staged source follower circuit. The drive MOS transistor DM2 has a drain terminal connected to a power source VDD terminal and a source terminal connected to a drain terminal of a load MOS transistor LM2 serving as current supplier to the MOS transistor DM2. The load MOS transistor LM2 has a gate terminal to receive the foregoing constant voltage VGG and a source terminal grounded through the fixed resistance RSS. The MOS transistors DM2, LM2 and the fixed resistance RSS constitute a second-staged source follower circuit.
Similarly, there are provided a drive MOS transistor DM3 corresponding to the drive MOS transistor DM2 and a load MOS transistor LM3 corresponding to the load MOS transistor LM2, to constitute a third-staged source follower circuit.
Namely, the drive MOS transistors DM1, DM2, DM3 have their drain terminals commonly connected to be applied by a drain voltage VDD (=15 V) from the drive power source 70. The load MOS transistors LM1, LM2, LM3 have their source terminals commonly connected and grounded through the source terminal resistance RSS. Meanwhile, the load MOS transistors LM1, LM2, LM3 have their gate terminals to be applied by a common gate voltage VGG. With this gate voltage VGG, the current flowing to the output section 50 is controlled in value. The drive MOS transistor DM3 has a source terminal (i.e. drain terminal of the load MOS transistor LM3) to which an output terminal of the output section 50 is provided to output an imaging signal Vout.
Incidentally, the MOS transistors DM1-DM3, LM1-LM3 are Nch-MOS transistors. The first-staged drive MOS transistor DM1 is an enhancement mode transistor while the other MOS transistors DM2, DM3, LM1-LM3 are depression mode transistors. The MOS transistors DM1-DM3, LM1-LM3 have a P-well being ground.
In the output section 50 thus configured, the potential caused on the FD terminal is reset with a period of a reset pulse φRG. Due to this, the drive MOS transistors DM1, DM2, DM3 operate in synchronism with a horizontal transfer clock. Upon each reset, the potential caused on the FD terminal is converted into a voltage signal and outputted it as an imaging signal Vout.
In the meanwhile, the solid-state imagers as above have recently been actively merchandised particularly as image sensors for still camera applications. Such an image sensor for a still camera performs signal storage operation in the pixel region for a comparatively long time, differently from the conventional one for a movie camera. For example, in the case of a movie camera, the signal storage time on the pixel is naturally limited in order to achieve a frame rate higher than a certain value, i.e. it is generally 1/30-th of a second. On the contrary, the still camera, free from restriction in frame rate, is allowed to have an increased signal storage period, i.e. the signal storage operation may be as long as several to several tens of seconds.
In the signal storage period, there is no need to apply a transfer clock pulse to the solid-state imaging device. However, the solid-state imaging device and camera must be placed in a standby state. Thus, the solid-state imaging device, at its VDD and VSUB terminals, is applied with a power voltage. This flows a current to the output section 50 connected to the VDD terminal even during a signal storage period, as mentioned above.
However, because no output operation of a CCD signal is made in this duration, there is, naturally, no need to flow a current for operating the output section 50. Namely, in the foregoing related art, the output section 50 consumes useless power during the signal storage period of the sensor sections 20. Meanwhile, such power consumption causes heat generation within the output section 50, resulting in occurrence of dark output variation in the vicinity of the output section 50. Such dark output variation occurs also in a solid-state imaging device for movie application. However, it is prominent particularly in the still-application device because of its longer storage period, and conspicuous on an imaging picture.
It can be considered as means for resolving the problem to provide a structure that, for example, switching means arranged in the external circuit is controlled to prevent a signal from flowing to the output section during a signal storage period. However, this approach incurs complication in the circuit configuration of a camera system.